SPRS439I – JUNE 2007 – REVISED MARCH 2011
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Table 6-63. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
NO.
M58 t
su(DRV-CKXL)
M59 t
h(CKXL-DRV)
M60 t
su(FXL-CKXL)
M61 t
c(CKX)
(1)
2P = 1/CLKG
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
2P
(1)
MASTER
MIN
30
1
MAX
SLAVE
MIN
8P – 10
8P – 10
16P + 10
16P
MAX
UNIT
ns
ns
ns
ns
Table 6-64. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
(1)
NO.
M53
M54
M56
M57
(1)
(2)
t
h(CKXH-FXL)
t
d(FXL-CKXL)
t
dis(CKXH-DXHZ)
t
d(FXL-DXV)
PARAMETER
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Disable time, DX high impedance following last
data bit from CLKX high
Delay time, FSX low to DX valid
MASTER
(2)
MIN
P
2P
(1)
P+6
6
7P + 6
4P + 6
MAX
SLAVE
MIN
MAX
UNIT
ns
ns
ns
ns
2P = 1/CLKG
C = CLKX low pulse width = P
D = CLKX high pulse width = P
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency
is LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
LSB
CLKX
M53
FSX
M56
DX
Bit 0
M58
DR
Bit 0
Bit(n-1)
M57
Bit(n-1)
M55
(n-2)
M59
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
M54
M60
MSB
M61
Figure 6-40. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
180
Electrical Specifications
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