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SPRS439I – JUNE 2007 – REVISED MARCH 2011
6.6
Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
a
c
d
f
h
r
su
t
v
w
access time
cycle time (period)
delay time
fall time
hold time
rise time
setup time
transition time
valid time
pulse duration (width)
Letters and symbols and their
meanings:
H
L
V
X
Z
High
Low
Valid
Unknown, changing, or don't care
level
High impedance
6.6.1
General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.6.2
Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
42
Ω
3.5 nH
Transmission Line
Z0 = 50
Ω
(Α)
Output
Under
Test
Device Pin
(B)
4.0 pF
1.85 pF
A.
B.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-4. 3.3-V Test Load Circuit
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Electrical Specifications
125
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