SPRS439I – JUNE 2007 – REVISED MARCH 2011
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XINTF
16-bits
External
wait-state
generator
CS
A(19:1)
A(0)
OE
WE
D(15:0)
XREADY
XCLKOUT
XZCS0/6/7
XA(19:1)
XA0/XWE1
XRD
XWE0
XD(15:0)
Figure 4-21. Typical 16-bit Data Bus XINTF Connections
XINTF
Low 16-bits
CS
A(18:0)
OE
WE
D(15:0)
High 16-bits
A(18:0)
CS
OE
WE
D(31:16)
XA0/XWE1
(select XWE1)
XD(31:16)
XZCS0/6/7
XA(19:1)
XRD
XWE0
XD(15:0)
External
wait-state
generator
XREADY
XCLKOUT
Figure 4-22. Typical 32-bit Data Bus XINTF Connections
Table 4-19. XINTF Configuration and Control Register Mapping
NAME
XTIMING0
XTIMING6
(1)
XTIMING7
XINTCNF2
(2)
XBANK
XREVISION
XRESET
(1)
(2)
ADDRESS
0x00−0B20
0x00−0B2C
0x00−0B2E
0x00−0B34
0x00−0B38
0x00−0B3A
0x00−0B3D
SIZE (x16)
2
2
2
2
1
1
1
DESCRIPTION
XINTF Timing Register, Zone 0
XINTF Timing Register, Zone 6
XINTF Timing Register, Zone 7
XINTF Configuration Register
XINTF Bank Control Register
XINTF Revision Register
XINTF Reset Register
XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
XINTCNF1 is reserved and not currently used.
108
Peripherals
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