TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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3
Functional Overview
M0 SARAM 1Kx16
(0-Wait)
L0 SARAM 4K x 16
(0-Wait, Dual Map)
OTP 1K x 16
M1 SARAM 1Kx16
(0-Wait)
L1 SARAM 4K x 16
(0-Wait, Dual Map)
Flash
256K x 16
8 Sectors
L2 SARAM 4K x 16
(0-Wait, Dual Map)
Code
Security
Module
L3 SARAM 4K x 16
(0-Wait, Dual Map)
TEST2
TEST1
L4 SARAM 4K x 16
(0-W Data, 1-W Prog)
Pump
PSWD
L5 SARAM 4K x 16
(0-W Data, 1-W Prog)
Boot ROM
8K x 16
Flash
Wrapper
L6 SARAM 4K x 16
(0-W Data, 1-W Prog)
L7 SARAM 4K x 16
(0-W Data, 1-W Prog)
Memory Bus
XD31:0
FPU
TCK
TDI
XHOLDA
XHOLD
XREADY
XR/W
TMS
32-bit CPU
(150 MHZ @ 1.9 V)
(100 MHz @ 1.8 V)
TDO
GPIO
MUX
88 GPIOs
TRST
EMU0
EMU1
XZCS0
XZCS7
XZCS6
XWE0
XCLKIN
X1
CPU Timer 0
XA0/XWE1
XA19:1
OSC,
DMA
6 Ch
PLL,
LPM,
WD
CPU Timer 1
CPU Timer 2
X2
XRS
XCLKOUT
XRD
PIE
(Interrupts)
88 GPIOs
8 External Interrupts
GPIO
MUX
A7:0
B7:0
XINTF
Memory Bus
12-Bit
ADC
2-S/H
DMA Bus
REFIN
32-bit peripheral bus
(DMA accessible)
32-bit peripheral bus
16-bit peripheral bus
FIFO
(16 Levels)
FIFO
(16 Levels)
FIFO
(16 Levels)
ePWM-1/../6
CAN-A/B
(32-mbox)
eQEP-1/2
McBSP-A/B
eCAP-1/../6
SCI-A/B/C
SPI-A
I2C
HRPWM-1/../6
GPIO MUX
88 GPIOs
Secure zone
Figure 3-1. Functional Block Diagram
34
Functional Overview
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TMS320F28232
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