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TMS320F28335ZJZS 参数 Datasheet PDF下载

TMS320F28335ZJZS图片预览
型号: TMS320F28335ZJZS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
SPRS439IJUNE 2007REVISED MARCH 2011  
www.ti.com  
4.7.3 ADC Calibration  
The ADC_cal() routine is programmed into TI reserved OTP memory by the factory. The boot ROM  
automatically calls the ADC_cal() routine to initialize the ADCREFSEL and ADCOFFTRIM registers with  
device specific calibration data. During normal operation, this process occurs automatically and no action  
is required by the user.  
If the boot ROM is bypassed by Code Composer Studio during the development process, then  
ADCREFSEL and ADCOFFTRIM must be initialized by the application. For working examples, see the  
ADC initialization in the C2833x, C2823x C/C++ Header Files and Peripheral Examples (literature number  
SPRC530). Methods for calling the ADC_cal() routine from an application are described in  
TMS320x2833x, F2823x Analog-to-Digital Converter (ADC) Module Reference Guide (literature number  
SPRU812).  
NOTE  
FAILURE TO INITIALIZE THESE REGISTERS WILL CAUSE THE ADC TO FUNCTION  
OUT OF SPECIFICATION.  
If the system is reset or the ADC module is reset using Bit 14 (RESET) from the ADC Control  
Register 1, the routine must be repeated.  
4.8 Multichannel Buffered Serial Port (McBSP) Module  
The McBSP module has the following features:  
Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices  
Full-duplex communication  
Double-buffered data registers that allow a continuous data stream  
Independent framing and clocking for receive and transmit  
External shift clock generation or an internal programmable frequency shift clock  
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits  
8-bit data transfers with LSB or MSB first  
Programmable polarity for both frame synchronization and data clocks  
Highly programmable internal clock and frame generation  
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially  
connected A/D and D/A devices  
Works with SPI-compatible devices  
The following application interfaces can be supported on the McBSP:  
T1/E1 framers  
IOM-2 compliant devices  
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)  
IIS-compliant devices  
SPI  
McBSP clock rate,  
CLKSRG  
1+ CLKGDV  
CLKG =  
(
)
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O  
buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less  
than the I/O buffer speed limit.  
NOTE  
See Section 6 for maximum I/O pin toggling speed.  
84  
Peripherals  
Copyright © 2007–2011, Texas Instruments Incorporated  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232