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TMS320F28335ZJZS 参数 Datasheet PDF下载

TMS320F28335ZJZS图片预览
型号: TMS320F28335ZJZS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
SPRS439IJUNE 2007REVISED MARCH 2011  
www.ti.com  
Trail  
(A)(B)  
(C)  
Active  
Lead  
XCLKOUT = XTIMCLK  
XCLKOUT = 1/2 XTIMCLK  
t
d(XCOH-XZCSL)  
t
d(XCOHL-XZCSH)  
XZCS0, XZCS6, XZCS7  
XA[0:19]  
t
d(XCOH-XA)  
t
d(XCOHL-XRDH)  
t
d(XCOHL-XRDL)  
XRD  
XWE0, XWE1(D)  
XR/W  
t
su(XD)XRD  
t
a(A)  
t
h(XD)XRD  
t
a(XRD)  
XD[0:31], XD[0:15]  
XREADY(E)  
DIN  
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an  
alignment cycle before an access to meet this requirement.  
B. During alignment cycles, all signals transition to their inactive state.  
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which  
remains high.  
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.  
E. For USEREADY = 0, the external XREADY input signal is ignored.  
Figure 6-23. Example Read Access  
XTIMING register parameters used for this example :  
XRDLEAD  
XRDACTIVE  
XRDTRAIL  
USEREADY  
X2TIMING  
XWRLEAD  
XWRACTIVE  
XWRTRAIL  
READYMODE  
1  
0  
0  
0
0
N/A(1)  
N/A(1)  
N/A(1)  
N/A(1)  
(1) N/A = Not applicable (or “Don’t care”) for this example  
156  
Electrical Specifications  
Copyright © 2007–2011, Texas Instruments Incorporated  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232