TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.3.3 Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is de-
vice-dependent; see Section Section 3.10) and connecting a crystal or ceramic resonator across X1 and
X2/CLKIN. The CPU clock frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The
multiply ratio is determined by the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30 Ω maximum and power dissipation of 1 mW. The connection of the required circuit,
consisting of the crystal and two load capacitors, is shown in Figure 5-2. The load capacitors, C1 and C2,
should be chosen such that the equation below is satisfied. CL (recommended value of 10 pF) in the
equation is the load specified for the crystal.
C1C2
CL +
(C1 ) C2)
Table 5-1. Input Clock Frequency Characteristics
MIN
MAX
Unit
fx
Input clock frequency
10(1)
20(2)
MHz
(1) This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz
(2) It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
X1
X2/CLKIN
Crystal
C1
C2
Figure 5-2. Internal Divide-By-Two Clock Option With External Crystal
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Electrical Specifications
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