TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.3 Electrical Characteristics
The electrical charactheristics are measured over recommended operating case temperature range (unless otherwise noted).
All values are typical unless otherwise specified.
PARAMETER
High-level output voltage(1)
Low-level output voltage(1)
TEST CONDITIONS
DVDD = 2.7 V to 3 V, IOH = -2 mA
DVDD = 3 V to 3.6 V, IOH = MAX
IOL = MAX
MIN
TYP
MAX UNIT
2.2
VOH
VOL
V
2.4
0.4
40
V
X2/CLKIN
– 40
– 10
µA
TRST, HPI16
HPIENA
TMS, TCK, TDI, HPI(2) With internal pullups
With internal pulldown
800
400
10
With internal pulldown, RS = 0
– 10
Input current (VI =
DVSS to DVDD
II
– 400
)
µA
A[17:0], D[15:0],
HD[7:0]
Bus holders enabled, DVDD = MAX(3)
– 275
– 5
275
5
All other input-only pins
IDDC
IDDP
Supply current, core CPU
Supply current, pins
CVDD = 1.6 V, fx = 160 ,(4)TC = 25°C
DVDD = 3.0 V, fx = 160 MHz,(4)TC = 25°C
PLL × 1 mode, 20 MHz input
TC = 25°C
60(5)
40(6)
2
mA
mA
IDLE2
Supply current,
standby
IDD
1
mA
IDLE3 Divide-by-two
mode, CLKIN stopped
TC = 100°C
30
5
Ci
Input capacitance
Output capacitance
pF
pF
Co
5
(1) All input and output voltage levels except RS, INT0-INT3, NMI, X2/CLKIN, CLKMD1-CLKMD3, BCLKRn, BCLKXn, HCS, HAS, HDS1,
HDS2, BIO, TCK, TRST, Dn, An, HDn are LVTTL-compatible.
(2) HPI input signals except for HPIENA and HPI16, when HPIENA = 0.
(3)
VIL(MIN) ≤VI ≤VIL(MAX) or VIH(MIN) ≤ VI ≤ VIH(MAX)
(4) Clock mode: PLL × 1 with external source
(5) This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program
being executed.
(6) This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is
performed, refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
5.3.1 Test Loading
Tester Pin Electronics
Data Sheet Timing Reference Point
42 W
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 W
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The
transmissionline is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data
sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. Tester Pin Electronics
54
Electrical Specifications
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