TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.5.5 Ready Timing for Externally Generated Wait States
Table 5-13 and Table 5-14 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-10, Figure 5-11, Figure 5-12, and Figure 5-13).
Table 5-13. Ready Timing Requirements for Externally Generated Wait States(1)
5416-120
5416-160
UNIT
MIN
7
MAX
tsu(RDY)
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low(2)
Hold time, READY after MSTRB low(2)
Valid time, READY after IOSTRB low(2)
Hold time, READY after IOSTRB low(2)
ns
ns
ns
ns
ns
ns
th(RDY)
0
tv(RDY)MSTRB
th(RDY)MSTRB
tv(RDY)IOSTRB
th(RDY)IOSTRB
4H – 4
4H – 4
4H
4H
(1) The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, as least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
(2) These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Table 5-14. Ready Switching Characteristics for Externally Generated Wait States(1)
5416-120
5416-160
PARAMETER
UNIT
MIN
0
MAX
td(MSCL)
td(MSCH)
Delay time, CLKOUT low to MSC low
Delay time, CLKOUT low to MSC high
4
4
ns
ns
0
(1) The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, as least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
Electrical Specifications
67
TI [ TEXAS INSTRUMENTS ]
