TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
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SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
V
, V
DDIO DD3VFL
V
, V
DDA2 DDAIO
(3.3 V)
V
, V
DD DD1A18,
V
DD2A18
(1.8 V)
XCLKIN
X1/X2
(A)
OSCCLK/8
XCLKOUT
XRS
User-Code Dependent
t
OSCST
t
w(RSL1)
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
User-Code Execution Phase
User-Code Dependent
t
d(EX)
(B)
h(boot-mode)
t
Boot-Mode
Pins
GPIO Pins as Input
Boot-ROM Execution Starts
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
Peripheral/GPIO Function
Based on Boot Code
I/O Pins
A. Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =
OSCCLK/8 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
Figure 6-5. Power-on Reset
Electrical Specifications
91
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