欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320VC5420PGE 参数 Datasheet PDF下载

TMS320VC5420PGE图片预览
型号: TMS320VC5420PGE
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [FIXED-POINT DIGITAL SIGNAL PROCESSOR]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 77 页 / 1023 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320VC5420PGE的Datasheet PDF文件第64页浏览型号TMS320VC5420PGE的Datasheet PDF文件第65页浏览型号TMS320VC5420PGE的Datasheet PDF文件第66页浏览型号TMS320VC5420PGE的Datasheet PDF文件第67页浏览型号TMS320VC5420PGE的Datasheet PDF文件第69页浏览型号TMS320VC5420PGE的Datasheet PDF文件第70页浏览型号TMS320VC5420PGE的Datasheet PDF文件第71页浏览型号TMS320VC5420PGE的Datasheet PDF文件第72页  
TMS320VC5420  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS080C – MARCH 1999 – REVISED APRIL 2000  
HPI16 timing (continued)  
timing requirements [H = 0.5t  
] (see Note 1 and Figure 35 – Figure 42)  
c(CO)  
MIN  
5
MAX  
UNIT  
ns  
†‡  
Setup time, HAD valid before DS falling edge  
t
t
su(HBV-DSL)  
†‡  
Hold time, HAD valid after DS falling edge  
5
ns  
h(DSL-HBV)  
t
t
t
t
t
t
t
t
t
Setup time, HAD valid before HAS falling edge  
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
su(HBV-HSL)  
h(HSL-HBV)  
su(HAV-DSH)  
su(HAV-DSL)  
h(DSH-HAV)  
su(HSL-DSL)  
h(HSL-DSL)  
w(DSL)  
Hold time, HAD valid after HAS falling edge  
Setup time, address valid before DS rising edge (nonmultiplexed write)  
Setup time, address valid before DS falling edge (nonmultiplexed mode)  
5
–4H – 5  
1
Hold time, address valid after DS rising edge (nonmultiplexed mode)  
Setup time, HAS low before DS falling edge  
5
Hold time, HAS low after DS falling edge  
2
Pulse duration, DS low  
30  
Pulse duration, DS high  
10  
w(DSH)  
Reads  
Writes  
Reads  
Writes  
Reads  
Writes  
12H  
14H  
18H  
20H  
26H  
28H  
Nonmultiplexed or multiplexed mode  
(no increment) with no DMA activity.  
Cycle time, DS rising edge to next DS Nonmultiplexed or multiplexed mode  
rising edge  
(noincrement)with16-bitDMAactivity.  
ns  
Nonmultiplexed or multiplexed mode  
(noincrement)with32-bitDMAactivity.  
t
c(DSH-DSH)  
Multiplexed (autoincrement) with no DMA  
activity.  
12H  
18H  
26H  
ns  
ns  
ns  
Cycle time, DS rising edge to next DS  
rising edge  
Multiplexed (autoincrement) with 16-bit DMA  
activity.  
(In autoincrement mode, WRITE tim-  
ings are the same as READ timings.)  
Multiplexed (autoincrement) with 32-bit DMA  
activity.  
Cycle time, DS rising edge to next DS rising edge writes to DSPINT and HINT  
8H  
10  
0
ns  
ns  
ns  
ns  
ns  
t
t
t
t
Setup time, HD valid before DS rising edge  
su(HDV-DSH)  
h(DSH-HDV)W  
su(SELV-DSL)  
h(DSH-SELV)  
Hold time, HD valid after DS rising edge, write  
Setup time, SELA/B valid before DS falling edge  
5
Hold time, SELA/B valid after DS Rising edge  
0
HAD stands for HCNTL0, HCNTL1, and HR/W.  
DS refers to the logical OR of HCS and HDS.  
68  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  
 复制成功!