TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
memory-mapped registers (continued)
Table 10. Peripheral Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
NAME
DRR20
DESCRIPTION
DEC
HEX
32
33
20
McBSP 0 Data Receive Register 2
DRR10
DXR20
DXR10
TIM
21
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer Register
34
22
35
23
36
24
PRD
37
25
Timer Period Register
TCR
38
26
Timer Control Register
—
39
27
Reserved
SWWSR
BSCR
—
40
28
Software Wait-State Register
Bank-Switching Control Register
Reserved
41
29
42
2A
SWCR
HPIC
—
43
2B
Software Wait-State Control Register
HPI Control Register (HMODE=0 only)
Reserved
44
2C
45–47
48
2D–2F
30
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
49
31
50
32
51
33
†
†
52
34
McBSP 2 Subbank Address Register
†
53
35
McBSP 2 Subbank Data Register
54–55
56
36–37
38
Reserved
SPSA0
SPSD0
—
McBSP 0 Subbank Address Register
†
57
39
McBSP 0 Subbank Data Register
Reserved
58–59
60
3A–3B
3C
GPIO
—
General-Purpose I/O Register
Reserved
61–63
64
3D–3F
40
DRR21
DRR11
DXR21
DXR11
—
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
Reserved
65
41
66
42
67
43
68–71
72
44–47
48
†
SPSA1
SPSD1
—
McBSP 1 Subbank Address Register
†
73
49
McBSP 1 Subbank Data Register
74–83
84
4A–53
54
Reserved
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
DMA Priority and Enable Control Register
‡
85
55
DMA Subbank Address Register
DMA Subbank Data Register with Autoincrement
‡
86
56
‡
DMA Subbank Data Register
87
57
88
58
Clock Mode Register (CLKMD)
Reserved
89–95
59–5F
†
‡
See Table 11 for a detailed description of the McBSP control registers and their subaddresses.
See Table 12 for a detailed description of the DMA sub-bank addressed registers.
33
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