TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
parallel I/O interface timing
switching characteristics over recommended operating conditions for a parallel I/O port read
†
(IOSTRB = 0) (see Figure 17)
PARAMETER
Delay time, CLKOUT low to address valid
MIN
–1
0
MAX
UNIT
ns
t
5
5
5
5
d(CLKL-A)
t
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to IOSTRB high
Hold time, address after CLKOUT low
ns
d(CLKH-ISTRBL)
t
0
ns
d(CLKH-ISTRBH)
t
–1
ns
h(A)IOR
†
Address and IS timings are included in timings referenced as address.
†
timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 t
] (see Figure 17)
c(CO)
MIN
MAX
5H–15
4H–14
UNIT
ns
t
t
t
t
t
Access time, read data access from address valid
Access time, read data access from IOSTRB low
Setup time, read data before CLKOUT high
Hold time, read data after CLKOUT high
a(A)IO
ns
a(ISTRBL)IO
su(D)IOR
10
0
ns
ns
h(D)IOR
Hold time, read data after IOSTRB high
0
ns
h(ISTRBH-D)R
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
t
h(A)IOR
d(CLKL-A)
PPA[17:0]
t
h(D)IOR
t
su(D)IOR
t
a(A)IO
PPD[15:0]
IOSTRB
t
h(ISTRBH-D)R
d(CLKH-ISTRBH)
t
a(ISTRBL)IO
t
t
d(CLKH-ISTRBL)
R/W
IS
1 Wait State
Figure 17. Parallel I/O Port Read (IOSTRB=0)
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443