TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
†‡§
TMS320VC5420 PGE PACKAGE
(TOP VIEW)
1
108
107
106
105
104
103
102
101
100
99
PPD7
PPA8
PPA0
PPA14
PPA15
2
3
V
SS
4
DV
PPA16
DD
5
PPA9
PPD1
PPA17
6
B_INT0
B_INT1
B_NMI
7
A_INT1
A_NMI
IOSTRB
A_GPIO2/BIO
A_GPIO1
A_RS
8
9
IS
10
11
12
13
14
15
16
B_GPIO2/BIO
B_GPIO1
B_GPIO0
B_BFSR1
B_BDR1
98
97
A_GPIO0
96
V
V
95
SS
SS
DD
94
CV
V
SS
DD
CV
93
A_BFSR1 17
A_BDR1 18
92
B_BCLKR1
B_BFSX1
91
A_BCLKR1 19
A_BFSX1 20
90
V
SS
89
B_BDX1
CV
V
21
88
B_BCLKX1
DD
SS
22
87
CV
V
SS
TEST
DD
A_BDX1 23
A_BCLKX1 24
A_XF 25
86
85
84
XIO
A_CLKOUT 26
VCO 27
83
B_RS
B_XF
82
TCK 28
TMS 29
TDI 30
TRST 31
81
B_CLKOUT
HMODE
HPIRS
PPA13
PPA12
80
79
78
EMU1/OFF 32
77
DV
33
V
DV
PPA11
PPA10
76
DD
SS
DD
A_INT0 34
EMU0 35
TDO
75
74
36
73
†
‡
NC = No internal connection
DV is the power supply for the I/O pins while CV
is the power supply for the core CPU. V
DD SS
is the ground for both the I/O
DD
pins and the core CPU.
§
Pin configuration shown for nonmultiplexed mode only. See the Pin Assignments for the TMS320VC5420PGE table for multiplexed
functions of specific pins.
3
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