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TMS320VC5407PGE 参数 Datasheet PDF下载

TMS320VC5407PGE图片预览
型号: TMS320VC5407PGE
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications  
5.14 Multichannel Buffered Serial Port (McBSP) Timing  
5.14.1 McBSP Transmit and Receive Timings  
Table 521 and Table 522 assume testing over recommended operating conditions (see Figure 521 and  
Figure 522).  
Table 521. McBSP Transmit and Receive Timing Requirements  
MIN  
MAX  
UNIT  
ns  
t
t
Cycle time, BCLKR/X  
BCLKR/X ext  
BCLKR/X ext  
BCLKR int  
BCLKR ext  
BCLKR int  
BCLKR ext  
BCLKR int  
BCLKR ext  
BCLKR int  
BCLKR ext  
BCLKX int  
BCLKX ext  
BCLKX int  
BCLKX ext  
BCLKR/X ext  
BCLKR/X ext  
4P  
c(BCKRX)  
Pulse duration, BCLKR/X high or BCLKR/X low  
2P1  
ns  
w(BCKRX)  
8
1
t
t
t
t
t
t
Setup time, external BFSR high before BCLKR low  
Hold time, external BFSR high after BCLKR low  
Setup time, BDR valid before BCLKR low  
ns  
ns  
ns  
ns  
ns  
ns  
su(BFRH-BCKRL)  
h(BCKRL-BFRH)  
su(BDRV-BCKRL)  
h(BCKRL-BDRV)  
su(BFXH-BCKXL)  
h(BCKXL-BFXH)  
1
2
7
1
2
Hold time, BDR valid after BCLKR low  
3
10  
1
Setup time, external BFSX high before BCLKX low  
Hold time, external BFSX high after BCLKX low  
0
2
t
t
Rise time, BCKR/X  
Fall time, BCKR/X  
6
6
ns  
ns  
r(BCKRX)  
f(BCKRX)  
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.  
P = 0.5 * processor clock  
92  
SPRS007D  
November 2001 Revised April 2004