Introduction
†
Table 2−1. Terminal Assignments for the 144-Pin BGA Package
SIGNAL
SIGNAL
SIGNAL
SIGNAL
QUADRANT 1
QUADRANT 2
QUADRANT 3
QUADRANT 4
BGA BALL #
A1
BGA BALL #
N13
M13
L12
BGA BALL #
N1
BGA BALL #
A13
A12
B11
A11
D10
C10
B10
A10
D9
V
SS
BCLKRX2
BDX2
V
SS
A19
A20
A22
B1
TX
N2
V
SS
C2
C1
D4
D3
D2
D1
E4
DV
HCNTL0
M3
N3
V
SS
DD
DV
V
SS
L13
V
SS
DV
DD
DD
A10
CLKMD1
CLKMD2
CLKMD3
HPI16
HD2
K10
K11
BCLKR0
BCLKR1
BFSR0
BFSR1
BDR0
K4
D6
HD7
A11
A12
A13
A14
A15
L4
D7
D8
K12
K13
J10
M4
N4
D9
K5
D10
D11
D12
HD4
D13
D14
D15
HD5
E3
TOUT
EMU0
EMU1/OFF
TDO
J11
HCNTL1
BDR1
L5
C9
E2
J12
M5
N5
B9
CV
E1
J13
BCLKX0
BCLKX1
A9
DD
HAS
F4
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
K6
D8
V
SS
V
SS
F3
TDI
V
SS
L6
C8
F2
TRST
HINT/TOUT1
CVDD
M6
N6
B8
CV
F1
TCK
A8
DD
HCS
HR/W
READY
PS
G2
G1
G3
G4
H1
H2
H3
H4
J1
TMS
BFSX0
M7
N7
CV
B7
DD
V
SS
BFSX1
V
SS
A7
CV
HRDY
L7
HDS1
C7
DD
HPIENA
DV
K7
V
SS
D7
DD
DS
V
SS
V
SS
N8
HDS2
DV
A6
IS
CLKOUT
HD3
X1
HD0
BDX0
BDX1
IACK
HBIL
NMI
M8
L8
B6
DD
R/W
A0
C6
MSTRB
IOSTRB
MSC
XF
F10
E13
E12
E11
K8
A1
A2
A3
HD6
A4
A5
A6
A7
A8
A9
D6
X2/CLKIN
RS
N9
A5
J2
M9
L9
B5
J3
D0
C5
HOLDA
IAQ
J4
D1
E10
D13
D12
D11
C13
C12
C11
B13
B12
INT0
INT1
INT2
INT3
K9
D5
K1
D2
N10
M10
L10
N11
M11
L11
N12
M12
A4
HOLD
BIO
K2
D3
B4
K3
D4
C4
MP/MC
L1
D5
CV
A3
DD
DV
L2
A16
HD1
B3
DD
V
SS
L3
V
SS
V
SS
CV
DD
C3
BDR2
M1
M2
A17
A18
RX
A21
A2
BFSRX2
V
SS
V
SS
B2
†
DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O pins and the
DD
DD
SS
core CPU.
16
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
