ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢄꢅ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
Pin Assignments for the TMS320VC5420PGE
(144-Pin Low-Profile Quad Flatpack) (Continued)
PRIMARY
SIGNAL NAME
SECONDARY
SIGNAL NAME
PIN
NO.
PRIMARY
SIGNAL NAME
SECONDARY
SIGNAL NAME
PIN
NO.
PPA10
DV
73
75
PPA11
74
76
V
SS
DD
PPA12
HPIRS
B_CLKOUT
B_RS
77
PPA13
HMODE
B_XF
XIO
78
79
80
81
82
83
84
TEST
85
V
86
SS
B_BCLKX1
CV
87
88
DD
B_BDX1
89
V
90
SS
B_BCLKR1
CV
B_BFSX1
91
92
V
SS
93
94
DD
B_BDR1
B_GPIO0
B_GPIO2/BIO
B_NMI
95
B_BFSR1
B_GPIO1
96
97
98
B_GPIO3
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
IS
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
B_INT1
PPA17
B_INT0
PPA16
V
SS
PPA15
PPA14
PPA6
PPA7
PPA4
HAS
HD3
DV
DD
PPA5
PPA1
B_HINT
HD2
PPD3
PPD2
B_BFSR2
B_BDR2
V
SS
CV
DD
B_BCLKR2
B_BDX2
B_BFSX2
B_BCLKX2
V
SS
AV
DD
V
SSA
NC
DV
CLKIN
DD
READY
HRDY
A_BCLKX2
CV
V
SS
DD
A_BCLKR2
A_BFSR2
A_BFSX2
PPD4
A_BDR2
A_BDX2
PPD6
HD6
HD5
HD4
HD0
PPD5
PPD0
143
V
SS
144
7
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