ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉꢄ ꢅ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢇꢍꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
HPI16 timing
†‡§
switching characteristics over recommended operating conditions
(see Figure 35 – Figure 42)
[H = 0.5t
]
c(CO)
PARAMETER
MIN
3
MAX
UNIT
§
t
d(DSL-HDD)
Delay time, DS low to HD driven
20
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
18H+20 – t
w(DSH)
t
< 18H
w(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
20
t
≥ 18H
w(DSH)
Case 1c: Memory access when
DMAC is active in 32-bit mode and
26H+20 – t
w(DSH)
w(DSH)
t
< 26H
Delay time, DS low to HDx valid for first
byte of an HPI read
w(DSH)
t
d(DSL-HDV1)
ns
Case 1d: Memory access when
DMAC is active in 32-bit mode and
20
t
≥ 26H
w(DSH)
Case 2a: Memory accesses when
DMAC is inactive and t < 10H
10H+20 – t
20
w(DSH)
Case 2b: Memory accesses when
DMAC is inactive and t ≥ 10H
w(DSH)
Case 3: Register accesses
Multiplexed reads with autoincrement. Prefetch completed.
No DMA channel active
20
20
t
t
3
ns
ns
d(DSL-HDV2)
12H+5
One or more 16-bit DMA channels
active
18H+5
§
Delay time, DS high to HRDY high
(writes and autoincrement reads)
d(DSH-HYH)
One or more 32-bit DMA channels
active
26H+5
4H + 5
Writes to DSPINT and HINT
7
10
5
ns
ns
ns
ns
ns
t
t
t
t
t
Valid time, HDx valid after HRDY high
v(HYH-HDV)
h(DSH-HDV)R
d(COH-HYH)
d(DSH-HYL)
d(COH−HTX)
§
Hold time, HD valid after DS rising edge, read
0
Delay time, CLKOUT rising edge to HRDY high
‡
Delay time, HDS or HCS high to HRDY low
Delay time, CLKOUT rising edge to HINT change
12
5
†
‡
§
HAD stands for HCNTL0, HCNTL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
68
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