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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
I/O port timing for externally generated wait states
†
timing requirements for externally generated wait states [H = 0.5 t
Figure 20)
] (see Figure 19 and
c(CO)
MIN
7
MAX
UNIT
ns
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
su(RDY)
0
ns
h(RDY)
‡
Valid time, READY after IOSTRB low
5H−8
ns
v(RDY)IOSTRB
h(RDY)IOSTRB
‡
Hold time, READY after IOSTRB low
5H
ns
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
‡
CLKOUT
PPA[17:0]
t
h(RDY)
t
su(RDY)
READY
IOSTRB
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
Wait State Generated
by READY
Wait
States
Generated
Internally
Figure 19. I/O Port Read With Externally Generated Wait States
53
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