ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢄꢅ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
external memory interface timing for one wait state
switching characteristics over recommended operating conditions for a one-wait-state memory
†
read (MSTRB = 0) (see Figure 13)
PARAMETER
MIN
−1
−1
−1
−1
−1
−1
MAX
UNIT
ns
‡
t
t
Delay time, CLKOUT low to address valid
5
6
4
4
5
6
d(CLKL-A)
§
Delay time, CLKOUT high (transition) to address valid
Delay time, CLKOUT low to MSTRB low
ns
d(CLKH-A)
t
ns
d(CLKL-MSL)
t
Delay time, CLKOUT low to MSTRB high
ns
d(CLKL-MSH)
‡
t
Hold time, address valid after CLKOUT low
ns
h(CLKL-A)R
h(CLKH-A)R
§
t
Hold time, address valid after CLKOUT high
ns
†
‡
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory read preceded by a memory read
In the case of a memory read preceded by a memory write
†
timing requirements for a one-wait-state memory read (MSTRB = 0) [H = 0.5 t
] (see Figure 13)
c(CO)
MIN
MAX
4H−15
4H−14
UNIT
ns
t
t
t
t
t
Access time, read data access from address valid (1 wait state required)
Access time, read data access from MSTRB low
Setup time, read data before CLKOUT low
a(A)M
ns
a(MSTRBL)
su(D)R
12
0
ns
Hold time, read data after CLKOUT low
ns
h(D)R
Hold time, read data after address invalid
0
ns
h(A-D)R
t
Hold time, read data after MSTRB high
0
ns
h(D)MSTRBH
†
Address, PS, and DS timings are all included in timings referenced as address.
45
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