Introduction
Table 2–1. Terminal Assignments for the 144-Pin BGA Package
†
SIGNAL
QUADRANT 1
VSS
A22
VSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
CVDD
HAS
VSS
VSS
CVDD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
VSS
BDR2
BFSRX2
BGA BALL #
A1
B1
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
G2
G1
G3
G4
H1
H2
H3
H4
J1
J2
J3
J4
K1
K2
K3
L1
L2
L3
M1
M2
SIGNAL
QUADRANT 2
BCLKRX2
BDX2
DVDD
VSS
CLKMD1
CLKMD2
CLKMD3
HPI16
HD2
TOUT
EMU0
EMU1/OFF
TDO
TDI
TRST
TCK
TMS
VSS
CVDD
HPIENA
VSS
CLKOUT
HD3
X1
X2/CLKIN
RS
D0
D1
D2
D3
D4
D5
A16
VSS
A17
A18
BGA BALL #
N13
M13
L12
L13
K10
K11
K12
K13
J10
J11
J12
J13
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
F10
E13
E12
E11
E10
D13
D12
D11
C13
C12
C11
B13
B12
SIGNAL
QUADRANT 3
VSS
TX
HCNTL0
VSS
BCLKR0
BCLKR1
BFSR0
BFSR1
BDR0
HCNTL1
BDR1
BCLKX0
BCLKX1
VSS
HINT/TOUT1
CVDD
BFSX0
BFSX1
HRDY
DVDD
VSS
HD0
BDX0
BDX1
IACK
HBIL
NMI
INT0
INT1
INT2
INT3
CVDD
HD1
VSS
RX
VSS
BGA BALL #
N1
N2
M3
N3
K4
L4
M4
N4
K5
L5
M5
N5
K6
L6
M6
N6
M7
N7
L7
K7
N8
M8
L8
K8
N9
M9
L9
K9
N10
M10
L10
N11
M11
L11
N12
M12
SIGNAL
QUADRANT 4
A19
A20
VSS
DVDD
D6
D7
D8
D9
D10
D11
D12
HD4
D13
D14
D15
HD5
CVDD
VSS
HDS1
VSS
HDS2
DVDD
A0
A1
A2
A3
HD6
A4
A5
A6
A7
A8
A9
CVDD
A21
VSS
BGA BALL #
A13
A12
B11
A11
D10
C10
B10
A10
D9
C9
B9
A9
D8
C8
B8
A8
B7
A7
C7
D7
A6
B6
C6
D6
A5
B5
C5
D5
A4
B4
C4
A3
B3
C3
A2
B2
† DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the
core CPU.
4
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
