TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states
timing requirements for externally generated wait states [H = 0.5 t
c(CO)
]
†
(see Figure 17, Figure 18,
Figure 19, and Figure 20)
MIN
tsu(RDY)
th(RDY)
tv(RDY)MSTRB
th(RDY)MSTRB
tv(RDY)IOSTRB
th(RDY)IOSTRB
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low‡
Hold time, READY after MSTRB low‡
Valid time, READY after IOSTRB low‡
Hold time, READY after IOSTRB low‡
6
0
4H–8
4H
5H–8
5H
MAX
UNIT
ns
ns
ns
ns
ns
ns
tv(MSCL)
Valid time, MSC low after CLKOUT low
–1
3
ns
tv(MSCH)
Valid time, MSC high after CLKOUT low
–1
3
ns
† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
CLKOUT
A[19:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait State
Generated
by READY
Wait States
Generated Internally
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 17. Memory Read With Externally Generated Wait States
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