TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145K
−
JULY 2000
−
REVISED AUGUST 2005
pin functions (continued)
†‡
(Continued)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
63
63
64
64
43
44
47
47
45
45
46
46
−
−
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
DESCRIPTION
CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI)
CANRX/IOPC7
CANTX/IOPC6
SCITXD/IOPA0
SCIRXD/IOPA1
SPICLK/IOPC4
SPISIMO/IOPC2
SPISOMI/IOPC3
SPISTE/IOPC5
SPICLK
IOPC4
SPISIMO
IOPC2
SPISOMI
IOPC3
SPISTE
IOPC5
CANRX
IOPC7
CANTX
IOPC6
70
70
72
72
25
26
35
35
30
30
32
32
33
33
49
49
50
50
17
18
24
24
21
21
22
22
23
23
−
49
−
50
17
18
24
24
21
21
22
22
23
23
CAN receive data or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
CAN transmit data or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
SCI asynchronous serial port transmit data or GPIO (↑)
SCI asynchronous serial port receive data or or
GPIO (↑)
SPI clock or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
SPI slave in, master out or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
SPI slave out, master in or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
SPI slave transmit enable (optional) or GPIO (↑)
transmit-enable
EXTERNAL INTERRUPTS, CLOCK
Device Reset (in) and Watchdog Reset (out).
Device reset. RS causes the device to terminate execution
and to set PC = 0. When RS is brought to a high level,
execution begins at location 0x0000 of program memory.
This pin is driven low by the DSP when a watchdog reset
occurs. During watchdog reset, the RS pin will be driven
low for the watchdog reset duration of 128 CLKIN cycles.
The output buffer of this pin is an open-drain with an
internal pullup (20
µA,
typical). It is recommended that this
pin be driven by an open-drain device. (↑)
Power drive protection interrupt input. This interrupt, when
activated, puts the PWM output pins (EVA) in the
high-impedance state should motor drive/power converter
abnormalities, such as overvoltage or overcurrent, etc.,
arise. PDPINTA is a falling-edge-sensitive interrupt. (↑)
RS
133
93
93
28
PDPINTA
7
6
6
36
†
‡
Bold, italicized pin names
indicate pin function after reset.
GPIO
−
General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
CCA
be isolated from the digital supply voltage (and V
SSA
from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (V , V
DD DDO
, V
SS
, or V
SSO
) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
−
Internal pullup
↓
−
Internal pulldown
(Typical active pullup/pulldown value is
±16 µA.)
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
13
TI [ TEXAS INSTRUMENTS ]
