TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012
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Table 6-56. McBSP Switching Characteristics(1) (2)
NO.
M1
M2
M3
M4
PARAMETER
MIN
MAX UNIT
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
2P
ns
(3)
(3)
tw(CKRXH)
tw(CKRXL)
td(CKRH-FRV)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
Delay time, CLKR high to internal FSR valid
D – 5
D + 5
ns
ns
ns
(3)
(3)
C – 5
C + 5
0
3
0
3
4
27
4
M5
M6
M7
td(CKXH-FXV)
tdis(CKXH-DXHZ)
td(CKXH-DXV)
Delay time, CLKX high to internal FSX valid
ns
ns
ns
27
8
Disable time, CLKX high to DX high impedance
following last data bit
14
9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
28
8
Delay time, CLKX high to DX valid
DXENA = 0
14
Only applies to first bit transmitted when DXENA = 1
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
P + 8
P + 14
M8
M9
ten(CKXH-DX)
Enable time, CLKX high to DX driven
DXENA = 0
CLKX int
CLKX ext
CLKX int
CLKX ext
0
6
ns
Only applies to first bit transmitted when DXENA = 1
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
P
P + 6
td(FXH-DXV)
Delay time, FSX high to DX valid
DXENA = 0
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
8
14
ns
ns
Only applies to first bit transmitted when DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode.
P + 8
P + 14
M10 ten(FXH-DX)
Enable time, FSX high to DX driven
DXENA = 0
0
6
Only applies to first bit transmitted when DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode
P
P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
176
Electrical Specifications
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