TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439M –JUNE 2007–REVISED AUGUST 2012
1
SPICLK
(clock polarity = 0)
2
4
3
SPICLK
(clock polarity = 1)
5
SPISIMO
SPISOMI
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing
end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit,
except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-18. SPI Master Mode External Timing (Clock Phase = 0)
Copyright © 2007–2012, Texas Instruments Incorporated
Electrical Specifications
145
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