TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439M –JUNE 2007–REVISED AUGUST 2012
XINTF
External
wait-state
generator
XREADY
16-bits
XCLKOUT
XZCS0, XZCS6, XZCS7
XA(19:1)
CS
A(19:1)
A(0)
XA0/XWE1
XRD
OE
WE
XWE0
D(15:0)
XD(15:0)
Figure 4-21. Typical 16-bit Data Bus XINTF Connections
XINTF
External
wait-state
generator
XREADY
Low 16-bits
XCLKOUT
CS
A(18:0)
OE
XA(19:1)
XRD
WE
XWE0
D(15:0)
XD(15:0)
High 16-bits
A(18:0)
XZCS0, XZCS6, XZCS7
CS
OE
WE
XA0/XWE1
(select XWE1)
D(31:16)
XD(31:16)
Figure 4-22. Typical 32-bit Data Bus XINTF Connections
Table 4-19. XINTF Configuration and Control Register Mapping
NAME
ADDRESS
0x00−0B20
0x00−0B2C
0x00−0B2E
0x00−0B34
0x00−0B38
0x00−0B3A
0x00−0B3D
SIZE (x16)
DESCRIPTION
XINTF Timing Register, Zone 0
XTIMING0
XTIMING6(1)
XTIMING7
XINTCNF2(2)
XBANK
2
2
2
2
1
1
1
XINTF Timing Register, Zone 6
XINTF Timing Register, Zone 7
XINTF Configuration Register
XINTF Bank Control Register
XINTF Revision Register
XREVISION
XRESET
XINTF Reset Register
(1) XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
(2) XINTCNF1 is reserved and not currently used.
Copyright © 2007–2012, Texas Instruments Incorporated
Peripherals
107
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