SPRS439M – JUNE 2007 – REVISED AUGUST 2012
(A)
(B)
Device
Status
Flushing Pipeline
Wake-up
Signal
(G)
(C)
(D)
STANDBY
STANDBY
(E)
(F)
Normal Execution
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A.
B.
IDLE instruction is executed to put the device into STANDBY mode.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
•
16 cycles, when DIVSEL = 00 or 01
•
32 cycles, when DIVSEL = 10
•
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is
in progress and its access time is longer than this number then it will fail. It is recommended to enter STANDBY
mode from SARAM without an XINTF access in progress.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
The external wake-up signal is driven active.
After a latency period, the STANDBY mode is exited.
Normal execution resumes. The device will respond to the interrupt (if enabled).
From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
C.
D.
E.
F.
G.
Figure 6-13. STANDBY Entry and Exit Timing Diagram
136
Electrical Specifications
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