TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
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SPRS439C–JUNE 2007–REVISED FEBRUARY 2008
4.8 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
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Compatible to McBSP in TMS320C54x™/TMS320C55x™ DSC devices
Full–duplex communication
Double–buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8–, 12–, 16–, 20–, 24–, or 32–bits
8–bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry–standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
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Works with SPI–compatible devices
The following application interfaces can be supported on the McBSP:
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T1/E1 framers
MVIP switching–compatible and ST–BUS–compliant devices including:
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MVIP framers
H.100 framers
SCSA framers
IOM–2 compliant devices
AC97–compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS–compliant devices
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McBSP clock rate,
CLKSRG
CLKG =
1+ CLKGDV
(
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where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O
buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit—20–MHz maximum.
Figure 4-11 shows the block diagram of the McBSP module.
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Peripherals
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