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SPRS174S – APRIL 2001 – REVISED MARCH 2011
6.30.4 ADC Power-Up Control Bit Timing
ADC Power Up Delay
PWDNBG
ADC Ready for Conversions
PWDNREF
t
d(BGR)
PWDNADC
t
d(PWD)
Request for
ADC Conversion
Figure 6-40. ADC Power-Up Control Bit Timing
Table 6-47. ADC Power-Up Delays
(1)
MIN
t
d(BGR)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) are to be set to 1 before the ADCPWDN bit is
enabled.
Delay time for power-down control to be stable. Bit 5 of the ADCTRL3 register
(ADCPWDN) is to be set to 1 before any ADC conversions are initiated.
7
20
TYP
8
50
1
MAX
10
UNIT
ms
µs
ms
t
d(PWD)
(1)
These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If
conversions are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at
the same time.
6.30.5 Detailed Description
6.30.5.1 Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP
is set to 2.0 V and ADCVREFM is set to 1.0 V.
6.30.5.2 Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at
a time. These inputs are software-selectable.
6.30.5.3 Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with
low power consumption.
6.30.5.4 Conversion Modes
The conversion can be performed in two different conversion modes:
• Sequential sampling mode (SMODE = 0)
• Simultaneous sampling mode (SMODE = 1)
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Electrical Specifications
145
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