TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.9.3 EMIFA Electrical Data/Timing
Table 6-24. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)
(see Figure 6-14 and Figure 6-15)
-400
-500
-600
NO.
UNIT
MIN
MAX
READS and WRITES
Pulse duration, EM_WAIT assertion and deassertion
READS
2
tw(EM_WAIT)
2E
ns
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
14 tsu(EMWAIT-EMOEH)
Setup time, EM_D[7:0] valid before EM_OE high
Hold time, EM_D[7:0] valid after EM_OE high
Setup time, EM_WAIT asserted before EM_OE high(2)
WRITES
TBD
TBD
ns
ns
ns
4E + TBD
28 tsu(EMWAIT-EMWEH)
Setup time, EM_WAIT asserted before EM_WE high(2)
4E + TBD
ns
(1) E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 600 MHz, use E = 10 ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
208
Peripheral Information and Electrical Specifications
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