TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.8 Interrupts
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 6-21. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 6-22
summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP
interrupt controller, see the TMS320DM643x DMP DSP Subsystem Reference Guide (literature number
SPRU978).
Table 6-21. DM6437 DSP System Event Mapping
DSP
DSP
SYSTEM
EVENT
SYSTEM
EVENT
ACRONYM
SOURCE
ACRONYM
SOURCE
NUMBER
NUMBER
0
EVT0
C64x+ Int Ctl 0
C64x+ Int Ctl 1
C64x+ Int Ctl 2
C64x+ Int Ctl 3
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO
1
EVT1
GPIO
2
EVT2
GPIO
3
EVT3
GPIO
4
TINTL0
TINTH0
TINTL1
TINTH1
WDINT
Timer 0 – TINT12
Timer 0 – TINT34
Timer 1 – TINT12
Timer 1 – TINT34
Timer 2 – TINT12
C64x+ EMC
GPIO
5
GPIO
6
GPIO
7
GPIO
8
GPIOBNK0
GPIOBNK1
GPIOBNK2
GPIOBNK3
GPIOBNK4
GPIOBNK5
GPIOBNK6
GPIO
9
EMU_DTDMA
GPIO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
GPIO
EMU_RTDXRX
EMU_RTDXTX
IDMAINT0
C64x+ RTDX
C64x+ RTDX
C64x+ EMC 0
C64x+ EMC 1
Reserved
GPIO
GPIO
GPIO
IDMAINT1
GPIO
Reserved
PWM0
PWM1
PWM2
I2C
Reserved
PWM0
Reserved
PWM1
Reserved
PWM2
Reserved
IICINT0
UARTINT0
UARTINT1
Reserved
UART0
UART1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VDINT0
VDINT1
VDINT2
HISTINT
H3AINT
PRVUINT
RSZINT
VPSS – CCDC 0
VPSS – CCDC 1
VPSS – CCDC 2
VPSS – Histogram
VPSS – AE/AWB/AF
VPSS – Previewer
VPSS – Resizer
Reserved
VENCINT
VPSS – VPBE (VENC)
INTERR
C64x+ Interrupt Controller Dropped CPU
Interrupt Event
32
96
33
34
35
36
37
38
39
40
41
42
Reserved
97
98
EMC_IDMAERR
C64x+ EMC Invalid IDMA Parameters
EDMA3CC_GINT
EDMA3CC_INT0
EDMA3CC_INT1
EDMA3CC_ERRINT
EDMA3TC_ERRINT0
EDMA3TC_ERRINT1
EDMA3TC_ERRINT2
PSCINT
EDMACC Global Interupt
EDMACC Interrupt Region 0
EDMACC Interrupt Region 1
EDMA CC Error
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
99
100
101
102
103
104
105
106
EDMA TC0 Error
EDMA TC1 Error
EDMA TC2 Error
PSC ALLINT
Reserved
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