TMS320C6678
Data Manual
SPRS691D—April 2013
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Release History
Revision Date
Description/Comments
SPRS691D April 2013
• Added Initial Startup row for CVDD in Recommended Operating Conditions table
• Added DDR3PLLCTL1 and PASSPLLCTL1 registers to Device Status Control Registers table
• Added CVDD and SmartReflex voltage parameter in SmartReflex switching table
• Added HOUT timing diagram in Host Interrupt Output section
• Added MPU Registers Reset Values section
• Corrected PASSCLK(N/P) max cycle time from 6.4 ns to 25 ns
• Corrected Reserved to be Assert local reset to all CorePacs in LRESET and NMI decoding table
• Corrected PASS PLL clock to SRIOSGMIICLK in the boot device values table for Ethernet.
• Updated the Timer numbering across the whole document
• Updated DDR3 PLL initialization sequence
SPRS691C February 2012 • Added TeraNet connection figures and added bridge numbers to the connection tables
• Changed TPCC to EDMA3CC and TPTC to EDMA3TC
• Changed chip level interrupt controller name from INTC to CIC
• Added the DDR3 PLL and PASS PLL Initialization Sequence
• Added DEVSPEED Register section
• Updated device frequency in the feature section
• Corrected the SPI, DDR3, and Hyperbridge config/data memory map addresses
• Restricted Output Divide of SECCTL Register to max value of divide by 2
SPRS691B August 2011
• Updated the timing and electrical sections of several peripherals
• Updated the core-specific and general-purpose timer numbers
• Updated the connection matrix tables in chapter 4 “System Interconnection”
• Updated device boot configuration tables and figures
• Updated DDR3 and PASS PLL timing figures
• Removed section 7.1 “Parameter Information”
SPRS691A July 2011
• Added sections: NMI and LRSET
• Added Pin Map diagrams
• Added MAINPLLCTL1, DDR3PLLCTL1 and PAPLLCTL1 registers
• Changed PLL diagrams of MAIN PLL, DDR3 PLL and PASS PLL
• Changed C66x DSP System PLL Configuration table to include 1000 MHz and 1250 MHz columns
• Corrected items in the Memory Map Summary table
• Changed all occurrences of PA_SS to Network Coprocessor
• Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR
SPRS691
November
2010
Initial release
For detailed revision information, see ‘‘Revision History’’ on page A-233.
2
Release History
Copyright 2013 Texas Instruments Incorporated
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