TMS320C6672
Data Manual
SPRS708C—February 2012
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Release History
Revision Date
Description/Comments
SPRS708C February 2012
• Added TeraNet connection figures and added bridge numbers to the connection tables
• ·Changed TPCC to EDMA3CC and TPTC to EDMA3TC
• ·Changed chip level interrupt controller name from INTC to CIC
• ·Added the DDR3 PLL and PASS PLL Initialization Sequence
• Added DEVSPEED Register section
• Updated device frequency in the feature section
• Corrected the SPI, DDR3, and Hyperbridge config/data memory map addresses
• Restricted Output Divide of SECCTL Register to max value of divide by 2
SPRS708B August 2011
• Updated the timing and electrical sections of several peripherals
• Updated the core-specific and general-purpose timer numbers
• Updated the connection matrix tables in chapter 4 “System Interconnection”
• Updated device boot configuration tables and figures
• Updated DDR3 and PASS PLL timing figures
• Removed section 7.1 “Parameter Information”
SPRS708A July 2011
• Added sections: NMI and LRSET
• Added Pin Map diagrams
• Added MAINPLLCTL1, DDR3PLLCTL1 and PAPLLCTL1 registers
• Changed PLL diagrams of MAIN PLL, DDR3 PLL and PASS PLL
• Changed C66x DSP System PLL Configuration table to include 1000 MHz and 1250 MHz columns
• Corrected items in the Memory Map Summary table
• Changed all occurrences of PA_SS to Network Coprocessor
• Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR
SPRS708 November 2010
Initial release
For detailed revision information, see ‘‘Revision History’’ on page A-220.
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Release History
Copyright 2012 Texas Instruments Incorporated
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