ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
L2 architecture expanded
Figure 2 shows the detail of the L2 architecture on the TMS320C6414T, TMS320C6415T, and
TMS320C6416T devices. For more information on the L2MODE bits, see the cache configuration (CCFG)
register bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature
number SPRU610).
L2MODE
010
L2 Memory
Block Base Address
000
001
011
111
0x0000 0000
768K-Byte SRAM
0x000C 0000
128K-Byte RAM
64K-Byte RAM
0x000E 0000
0x000F 0000
32K-Byte RAM
32K-Byte RAM
0x000F 8000
0x000F FFFF
Figure 2. TMS320C6414T/C6415T/C6416T L2 Architecture Memory Configuration
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