The TMP75 features three address pins allowing up to eight
devices to be connected per bus. Pin logic levels are de-
scribed in Table XII. The address pins of the TMP175 and
TMP75 are read after reset, at start of communication, or in
response to a Two-Wire address acquire request. Following
reading the state of the pins the address is latched to minimize
power dissipation associated with detection.
sequence. If repeated reads from the same register are
desired, it is not necessary to continually send the Pointer
Register bytes, as the TMP175 and TMP75 will remember
the Pointer Register value until it is changed by the next write
operation.
SLAVE MODE OPERATIONS
The TMP175 and TMP75 can operate as slave receivers or
slave transmitters.
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
SLAVE ADDRESS
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
Slave Receiver Mode:
The first byte transmitted by the master is the slave address,
with the R/W bit LOW. The TMP175 or TMP75 then acknow-
ledges reception of a valid address. The next byte transmitted
by the master is the Pointer Register. The TMP175 or TMP75
then acknowledges reception of the Pointer Register byte. The
next byte or bytes are written to the register addressed by the
Pointer register. The TMP175 and TMP75 will acknowledge
reception of each data byte. The master may terminate data
transfer by generating a START or STOP condition.
TABLE XII. Address Pins and Slave Addresses for TMP75.
BUS OVERVIEW
The device that initiates the transfer is called a
master,
and
the devices controlled by the master are
slaves.
The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions.
To address a specific device, a START condition is initiated,
indicated by pulling the data-line (SDA) from a HIGH to LOW
logic level while SCL is HIGH. All slaves on the bus shift in the
slave address byte, with the last bit indicating whether a read
or write operation is intended. During the ninth clock pulse,
the slave being addressed responds to the master by gener-
ating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock pulses
followed by an Acknowledge Bit. During data transfer SDA
must remain stable while SCL is HIGH, as any change in SDA
while SCL is HIGH will be interpreted as a control signal.
Once all data has been transferred, the master generates a
STOP condition indicated by pulling SDA from LOW to HIGH,
while SCL is HIGH.
Slave Transmitter Mode:
The first byte is transmitted by the master and is the slave
address, with the R/W bit HIGH. The slave acknowledges
reception of a valid slave address. The next byte is transmit-
ted by the slave and is the most significant byte of the
register indicated by the Pointer Register. The master ac-
knowledges reception of the data byte. The next byte trans-
mitted by the slave is the least significant byte. The master
acknowledges reception of the data byte. The master may
terminate data transfer by generating a Not-Acknowledge on
reception of any data byte, or generating a START or STOP
condition.
SMBus ALERT FUNCTION
The TMP175 and TMP75 support the SMBus Alert function.
When the TMP75 and TMP175 are operating in Interrupt
Mode (TM = 1), the ALERT pin of the TMP75 or TMP175 may
be connected as an SMBus Alert signal. When a master
senses that an ALERT condition is present on the ALERT
line, the master sends an SMBus Alert command (00011001)
on the bus. If the ALERT pin of the TMP75 or TMP175 is
active, the devices will acknowledge the SMBus Alert com-
mand and respond by returning its slave address on the SDA
line. The eighth bit (LSB) of the slave address byte will
indicate if the temperature exceeding T
HIGH
or falling below
T
LOW
caused the ALERT condition. This bit will be HIGH if the
temperature is greater than or equal to T
HIGH
. This bit will be
LOW if the temperature is less than T
LOW
. Refer to Figure 8
for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert
command, arbitration during the slave address portion of the
SMBus Alert command will determine which device will clear
its ALERT status. If the TMP75 or TMP175 wins the arbitra-
tion, its ALERT pin will become inactive at the completion of
the SMBus Alert command. If the TMP75 or TMP175 loses
the arbitration, its ALERT pin will remain active.
WRITING/READING TO THE TMP175 AND TMP75
Accessing a particular register on the TMP175 and TMP75 is
accomplished by writing the appropriate value to the Pointer
Register. The value for the Pointer Register is the first byte
transferred after the slave address byte with the R/W bit
LOW. Every write operation to the TMP175 and TMP75
requires a value for the Pointer Register. (Refer to Figure 5.)
When reading from the TMP175 and TMP75, the last value
stored in the Pointer Register by a write operation is used to
determine which register is read by a read operation. To
change the register pointer for a read operation, a new value
must be written to the Pointer Register. This is accomplished
by issuing a slave address byte with the R/W bit LOW,
followed by the Pointer Register Byte. No additional data is
required. The master can then generate a START condition
and send the slave address byte with the R/W bit HIGH to
initiate the read command. See Figure 7 for details of this
8
TMP175, 75
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