TMP175
TMP75
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SBOS288J − JANUARY 2004 − REVISED DECEMBER 2007
The TMP175 features three address pins to allow up to 27
devices to be addressed on a single bus interface.
Table 11 describes the pin logic levels used to properly
connect up to 27 devices. ‘1’ indicates the pin is connected
to the supply (V
CC
); ‘0’ indicates the pin is connected to
GND;
Float
indicates the pin is left unconnected. The state
of pins A0, A1, and A2 is sampled on every bus
communication and should be set prior to any activity on
the interface.
The TMP75 features three address pins allowing up to
eight devices to be connected per bus. Pin logic levels are
described in Table 12. The address pins of the TMP175
and TMP75 are read after reset, at start of communication,
or in response to a Two-Wire address acquire request.
Following reading the state of the pins the address is
latched to minimize power dissipation associated with
detection.
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
SLAVE ADDRESS
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
Table 12. Address Pins and Slave Addresses for
the TMP75
BUS OVERVIEW
The device that initiates the transfer is called a
master,
and
the devices controlled by the master are
slaves.
The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions.
To address a specific device, a START condition is
initiated, indicated by pulling the data-line (SDA) from a
HIGH to LOW logic level while SCL is HIGH. All slaves on
the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended.
During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge
and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock
pulses followed by an Acknowledge Bit. During data
transfer SDA must remain stable while SCL is HIGH, as
any change in SDA while SCL is HIGH will be interpreted
as a control signal.
Once all data has been transferred, the master generates
a STOP condition indicated by pulling SDA from LOW to
HIGH, while SCL is HIGH.
A2
0
0
0
0
1
1
1
1
Float
Float
Float
Float
Float
Float
Float
Float
0
0
1
1
0
0
1
1
0
1
Float
A1
0
0
1
1
0
0
1
1
0
0
0
1
1
1
Float
Float
Float
Float
Float
Float
0
1
0
1
Float
Float
Float
A0
0
1
0
1
0
1
0
1
0
Float
1
0
Float
1
0
1
0
1
0
1
Float
Float
Float
Float
Float
Float
Float
SLAVE ADDRESS
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110101
0110110
0110111
WRITING/READING TO THE TMP175 AND
TMP75
Accessing a particular register on the TMP175 and TMP75
is accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is the
first byte transferred after the slave address byte with the
R/W bit LOW. Every write operation to the TMP175 and
TMP75 requires a value for the Pointer Register. (Refer to
Figure 5.)
Table 11. Address Pins and Slave Addresses for
the TMP175
8
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