2.4.3
tw(5)
tw(6)
tc(3)
tsu(4)
tsu(5)
th(4)
tw(7)
tw(8)
Three-Wire Control Interface (SDIN)
PARAMETER
High
Clock pulse duration, SCLK
Clock period, SCLK
Clock rising edge to CS rising edge, SCLK
Setup time, SDIN to SCLK
Hold time, SCLK to SDIN
High
Pulse duration, CS
Low
tw(8)
CS
tc(3)
tw(5)
SCLK
tsu(5)
DIN
th(4)
LSB
tw(6)
tsu(4)
Low
MIN
20
20
80
60
20
20
20
20
ns
ns
ns
ns
ns
ns
TYP
MAX
UNIT
Figure 2−4. Three-Wire Control Interface Timing Requirements
2.4.4
Two-Wire Control Interface
PARAMETER
MIN
1.3
600
0
600
600
900
100
300
300
600
0
tw(10)
tsp
50
400
TYP
MAX
UNIT
µs
ns
kHz
ns
ns
ns
ns
ns
ns
ns
ns
High
Low
tw(9)
Clock pulse duration, SCLK
tw(10)
f(sf)
th(5)
tsu(6)
th(6)
tsu(7)
tr
tf
tsu(8)
tsp
Clock frequency, SCLK
Hold time (start condition)
Setup time (start condition)
Data hold time
Data setup time
Rise time, SDIN, SCLK
Fall time, SDIN, SCLK
Setup time (stop condition)
Pulse width of spikes suppressed by input filter
tw(9)
SCLK
th(5)
DIN
th(6)
tsu(7)
tsu(8)
Figure 2−5. Two-Wire Control Interface Timing Requirements
2−7
TI [ TEXAS INSTRUMENTS ]
