2.4 Digital-Interface Timing
PARAMETER
MIN
18
TYP
MAX
UNIT
t
t
t
High
Low
w(1)
w(2)
c(1)
System-clock pulse duration, MCLK/XTI
ns
ns
18
System-clock period, MCLK/XTI
Duty cycle, MCLK/XTI
54
40/60%
0
60/40%
10
t
Propagation delay, CLKOUT
ns
pd(1)
t
c(1)
t
t
w(2)
w(1)
MCLK/XTI
CLKOUT
t
pd(1)
CLKOUT
(Div 2)
Figure 2−1. System-Clock Timing Requirements
2.4.1 Audio Interface (Master Mode)
PARAMETER
MIN
TYP
MAX
10
UNIT
ns
t
t
t
t
Propagation delay, LRCIN/LRCOUT
Propagation delay, DOUT
Setup time, DIN
0
0
pd(2)
pd(3)
su(1)
h(1)
10
ns
10
10
ns
Hold time, DIN
ns
BCLK
t
pd(2)
LRCIN
LRCOUT
t
pd(3)
DOUT
DIN
t
t
h(1)
su(1)
Figure 2−2. Master-Mode Timing Requirements
2−5