The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle, acknowledging
the data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a
rising edge on SDIN when SCLK is high (see Figure 3-2).
The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block:
B[15:9]
B[8:0]
Control Address Bits
Control Data Bits
Start
Stop
1
9
9
7
8
1
1
8
8
9
SCLK
SDI
ADDR R/W ACK B15 − B8 ACK B7 − B0 ACK
Figure 3−2. 2-Wire Compatible Timing
3.1.3 Register Map
The TLV320AIC23B has the following set of registers, which are used to program the modes of operation.
ADDRESS
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001111
REGISTER
Left line input channel volume control
Right line input channel volume control
Left channel headphone volume control
Right channel headphone volume control
Analog audio path control
Digital audio path control
Power down control
Digital audio interface format
Sample rate control
Digital interface activation
Reset register
Left line input channel volume control (Address: 0000000)
BIT
D8
LRS
0
D7
LIM
1
D6
X
D5
X
D4
LIV4
1
D3
LIV3
0
D2
LIV2
1
D1
LIV1
1
D0
LIV0
1
Function
Default
0
0
LRS
Left/right line simultaneous volume/mute update
Simultaneous update
Left line input mute
0 = Disabled
0 = Normal
1 = Enabled
1 = Muted
LIM
LIV[4:0]
Left line input volume control (10111 = 0 dB default)
11111 = +12 dB down to 00000 = –34.5 dB in 1.5-dB steps
Reserved
X
3−2
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