TLC7226C, TLC7226I, TLC7226M
QUADRUPLE 8 BIT DIGITAL TO ANALOG CONVERTERS
SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
PRINCIPLES OF OPERATION
AGND bias for positive output offset (continued)
Vref
TLC7226†
VI
_
2
AGND
5
Vbias
3
VSS
6
DGND
DAC A
+
OUTA
VDD
4
18
† Digital inputs omitted for clarity.
Figure 5. AGND Bias Circuit
interface logic information
Address lines A0 and A1 select which DAC accepts data from the input port. Table 2 shows the operations of
the four DACs. Figure 6 shows the input control logic. When the WR signal is low, the input latches of the
selected DAC are transparent and the output responds to activity on the data bus. The data is latched into the
addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value
corresponding to the data held in their respective latches.
Table 2. Function Table
CONTROL INPUTS
WR
H
L
↑
L
↑
L
↑
L
↑
L = low,
A1
X
L
L
L
L
H
H
H
H
H = high,
A2
X
L
L
H
H
L
L
H
H
OPERATION
No operation
Device not selected
DAC A transparent
DAC A latched
DAC B transparent
DAC B latched
DAC C transparent
DAC C latched
DAC D transparent
DAC D latched
X = irrelevant
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
