TLC5945
www.ti.com
SLVS755–MARCH 2007
PRINCIPLES OF OPERATION
SERIAL INTERFACE
The TLC5945 has a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK
signal shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of
XLAT signal latches the serial data to the internal registers. The internal registers are level-triggered latches of
XLAT signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending
on the programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle.
Although new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the
grayscale data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the
existing grayscale data. Figure 6 shows the timing chart. More than two TLC5945s can be connected in series
by connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two
TLC5945s is shown in Figure 7. The SOUT pin can also be connected to the controller to receive status
information from TLC5945 as shown in Figure 16.
MODE
DC Data Input Mode
GS Data Input Mode
t
t
h3
su3
t
wh2
XLAT
1st GS Data Input Cycle
2nd GS Data Input Cycle
DC
MSB
DC
LSB
GS1
MSB
GS1
GS2
MSB
GS2
LSB
GS3
MSB
SIN
LSB
su1
192
t
t
t
t
t
su2
su0
h1
t
h2
t
wh0
h0
193
1
192
96
1
193
1
1
t
SCLK
SOUT
BLANK
GSCLK
t
pd0
wl0
SID2
MSB-1
GS1
MSB
SID1
SID1
MSB MSB-1
SID2
MSB
DC
-
MSB
GS2
MSB
SID1
LSB
-
-
t
wh3
1st GS Data Output Cycle
2nd GS Data Output Cycle
t
t
t
wh1
su4
h4
t
su5
1
4096
1
t
t
pd3
wl1
T
t
t
gsclk
pd4
pd1
t
pd3
OUT0
(current)
t
t
outon
pd3
OUT1
(current)
OUT15
(current)
t
pd2
XERR
Figure 6. Serial Data Input Timing Chart
SIN(a)
SIN
SIN
SOUT(b)
SOUT
SOUT
TLC5945 (a)
TLC5945 (b)
SCLK, XLAT,
BLANK,
GSCLK,
MODE
Figure 7. Cascading Two TLC5945 Devices
11
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