TLC5620C, TLC5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001
functional block diagram
REFA
2
+
–
8
REFB
3
+
–
8
REFC
4
+
–
8
REFD
5
+
–
8
Latch
Latch
8
DAC
×
2
+
–
9
DACD
Latch
Latch
8
Latch
Latch
8
Latch
Latch
8
DAC
×
2
+
–
12
DACA
DAC
×
2
+
–
11
DACB
DAC
×
2
+
–
10
DACC
CLK 7
6
DATA
LOAD 8
Serial
Interface
13
LDAC
Power-On
Reset
Terminal Functions
TERMINAL
NAME
CLK
DACA
DACB
DACC
DACD
DATA
NO.
7
12
11
10
9
6
I/O
I
O
O
O
O
I
DESCRIPTION
Serial interface clock. The input digital data is shifted into the serial interface
register on the falling edge of the clock applied to the CLK terminal.
DAC A analog output
DAC B analog output
DAC C analog output
DAC D analog output
Serial interface digital data input. The digital code for the DAC is clocked into the
serial interface register serially. Each data bit is clocked into the register on the
falling edge of the clock signal.
Ground return and reference terminal
Load DAC. When the LDAC signal is high, no DAC output updates occur when
the input digital data is read into the serial interface. The DAC outputs are only
updated when LDAC is taken from high to low.
Serial Interface load control. When LDAC is low, the falling edge of the LOAD
signal latches the digital data into the output latch and immediately produces the
analog voltage at the DAC output terminal.
Reference voltage input to DAC A. This voltage defines the output analog range.
Reference voltage input to DAC B. This voltage defines the output analog range.
Reference voltage input to DAC C. This voltage defines the output analog range.
Reference voltage input to DAC D. This voltage defines the output analog range.
Positive supply voltage
GND
LDAC
1
13
I
I
LOAD
8
I
REFA
REFB
REFC
REFD
VDD
2
3
4
5
14
I
I
I
I
I
2
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