TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
recommended operating conditions
TLC548
MIN
Supply voltage, VCC
Positive reference voltage, Vref+ (see Note 3)
Negative reference voltage, Vref – (see Note 3)
Differential reference voltage, Vref+, Vref – (see Note 3)
Analog input voltage (see Note 3)
High-level control input voltage, VIH (for VCC = 4.75 V to 5.5 V)
Low-level control input voltage, VIL (for VCC = 4.75 V to 5.5 V)
Input/output clock frequency, fclock(I/O) (for VCC = 4.75 V to 5.5 V)
Input/output clock high, twH(I/O) (for VCC = 4.75 V to 5.5 V)
Input/output clock low, twL(I/O) (for VCC = 4.75 V to 5.5 V)
Input/output clock transition time, tt(I/O)
(for VCC = 4.75 V to 5.5 V) (see Note 4 and Operating Sequence)
Duration of CS input high state during conversion, twH(CS)
(for VCC = 4.75 V to 5.5 V) (see Operating Sequence)
Setup time, CS low before first I/O CLOCK, tsu(CS)
(for VCC = 4.75 V to 5.5 V) (see Note 5)
TLC548C, TLC549C
TLC548I, TLC549I
17
1.4
0
– 40
70
85
0
200
200
100
17
1.4
0
– 40
70
85
3
2.5
– 0.1
1
0
2
0.8
2.048
0
404
404
100
NOM
5
MAX
6
MIN
3
2.5
–0.1
1
0
2
0.8
1.1
TLC549
NOM
5
MAX
6
UNIT
V
V
V
V
V
V
V
MHz
ns
ns
ns
µs
µs
°C
VCC VCC+0.1
0
2.5
VCC VCC+0.2
VCC
VCC VCC+0.1
0
2.5
VCC VCC+0.2
VCC
NOTES: 3. Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied
to REF– convert to all zeros (00000000). For proper operation, the positive reference voltage Vref+, must be at least 1 V greater than
the negative reference voltage, Vref–. In addition, unadjusted errors may increase as the differential reference voltage, Vref+ – Vref– ,
falls below 4.75 V.
4. This is the time required for the I/O CLOCK input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2
µs
for remote data acquisition
applications in which the sensor and the ADC are placed several feet away from the controlling microprocessor.
5. To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internal
system clock after CS↓ before responding to control input signals. This CS setup time is given by the ten and tsu(CS) specifications.
4
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•
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