TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
11
12
Access Cycle B
DATA
OUT
A11
A10
A9
A8
A7
A6
Sample Cycle B
A5
A4
A1
A0
MSB
DATA
INPUT
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t(conv)
A/D Conversion
Interval
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 12-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
11
12
1
Access Cycle B
DATA
OUT
A11
A10
A9
A8
A7
A6
Sample Cycle B
A5
A4
A1
A0
B11
Low Level
DATA
INPUT
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Initialize
t(conv)
A/D Conversion
Interval
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MSB
Previous Conversion Data
LSB
Initialize
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Hi-Z State
1
B11
ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎ
C7
C7
9
TI [ TEXAS INSTRUMENTS ]
