TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
analog inputs and test modes (continued)
Table 2. Analog-Channel-Select Address
ANALOG INPUT
SELECTED
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VALUE SHIFTED INTO
ADDRESS INPUT
BINARY
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
HEX
0
1
2
3
4
5
6
7
8
9
A
Table 3. Test-Mode-Select Address
INTERNAL
SELF-TEST
VOLTAGE
SELECTED†
Vref+ – Vref–
2
Vref–
Vref+
VALUE SHIFTED INTO
ADDRESS INPUT
BINARY
1011
1100
1101
HEX
B
C
D
200
000
3FF
OUTPUT RESULT (HEX)‡
† Vref+ is the voltage applied to the REF+ input, and Vref– is the voltage applied to the REF–
input.
‡ The output results shown are the ideal values and vary with the reference stability and
with internal offsets.
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S
C
switch and all S
T
switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all S
T
and S
C
switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF –)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF –. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half V
CC
), a 0 bit is placed in
the output register and the 512-weight capacitor is switched to REF –. If the voltage at the summing node is less
than the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains
connected to REF + through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.
6
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