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TL16C752BPTR 参数 Datasheet PDF下载

TL16C752BPTR图片预览
型号: TL16C752BPTR
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V双64字节FIFO的UART [3.3-V DUAL UART WITH 64-BYTE FIFO]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
文件页数/大小: 36 页 / 503 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TL16C752B  
3.3-V DUAL UART WITH 64-BYTE FIFO  
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000  
functional description (continued)  
trigger levels  
The TL16C752B provides independent selectable and programmable trigger levels for both receiver and  
transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so,  
in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR.  
The programmable trigger levels are available via the TLR.  
hardware flow control  
Hardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled/  
disabled independently by programming EFR[7:6].  
With auto-CTS, CTS must be active before the UART can transmit data.  
Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and deactivates  
the RTS output when the RX FIFO is sufficiently full. The halt and resume trigger levels in the TCR determine  
the levels at which RTS is activated/deactivated.  
If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur  
unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control.  
If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.  
auto-RTS  
Auto-RTS data flow control originates in the receiver block (see functional block diagram). Figure 1 shows RTS  
functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the  
RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached,  
RTS is deasserted. The sending device (e.g., another UART) may send an additional byte after the trigger level  
is reached (assuming the sending UART has another byte to send) because it may not recognize the  
deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the  
receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This reassertion allows the sending  
device to resume transmission.  
Start  
Byte N  
Stop  
Start  
Byte N+1  
Stop  
Start  
RX  
RTS  
IOR  
1
2
N
N+1  
NOTES: 1. N = receiver FIFO trigger level  
2. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.  
Figure 1. RTS Functional Timing  
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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