TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Writeinput(activelowstrobe). AlowtohightransitiononIOWwilltransferthecontentsofthedatabus(D0–D7)
from the external CPU to an internal register that is defined by address bits A0–A2 and CSA and CSB
IOW
15
I
User defined outputs. This function is associated with individual channels A and B. The state of these pins is
defined by the user through the software settings of the MCR register, bit 3. INTA–B are set to active mode
and OP to a logic 0 when the MCR–3 is set to a logic 1. INTA–B are set to the 3-state mode and OP to a logic
1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit 3). The output of these two pins
is high after reset.
OPA, OPB
32, 9
0
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and the
receiver input will be disabled during reset time. See TL16C752B external reset conditions for initialization
details. RESET is an active-high input.
RESET
36
I
I
Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic low
onthesepinsindicatesthemodemhasreceivedaringingsignalfromthetelephoneline. Alowtohightransition
on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in
the modem status register (MSR)
RIA, RIB
41, 21
Request to send (active low). These outputs are associated with individual UART channels A and B. A low on
the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control
register (MCR bit 1) sets these pins to low, indicating data is available. After a reset, these pins are set to high.
These pins only affects the transmit and receive operation when auto RTS function is enabled through the
enhanced feature register (EFR) bit 6, for hardware flow control operation.
RTSA, RTSB
RXA, RXB
33, 22
5, 4
O
I
Receive data input. These inputs are associated with individual serial channel data to the 752B. During the
local loopback mode, these RX input pins are disabled and TX data is internally connected to the UART RX
input internally.
RXRDYA,
RXRDYB
Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a timeout
interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.
31, 18
7, 8
O
O
Transmitdata. Theseoutputsareassociatedwithindividualserialtransmitchanneldatafromthe752B. During
thelocalloopbackmode, theTXinputpinisdisabledandTXdataisinternallyconnectedtotheUARTRXinput.
TXA, TXB
TXRDYA,
TXRDYB
Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level numbers of spaces
available. They go high when the TX buffer is full.
43, 6
42
O
I
V
CC
Power supply inputs.
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can
be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 10). Alternatively,
an external clock can be connected to XTAL1 to provide custom data rates.
XTAL1
XTAL2
13
14
I
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output
or buffered a clock output.
O
3
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