TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
functional description (continued)
polled mode operation
In polled mode (IER[3:0]=0000) the status of the receiver and transmitter can be checked by polling the line
status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of
thereceiverandtransmitterisautomaticallyknownbymeansofinterruptssenttotheCPU. Figure6showsFIFO
polled mode operation.
LSR
IOW/IOR
Processor
IER
0
0
0
0
THR
RHR
Figure 6. FIFO Polled Mode Operation
DMA signalling
There are two modes of DMA operation: DMA mode 0 or 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[0]=0) DMA occurs in single character transfers. In DMA mode 1 multi-
character (or block) DMA transfers are managed to relieve the processor for longer periods of time.
single DMA transfers (DMA mode0/FIFO disable)
Transmitter: When empty, the TXRDY signal becomes active. TXRDY will go inactive after one character has
been loaded into it.
Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the
receiver is empty.
Figure 7 shows TXRDY and RXRDY in DMA mode0/FIFO disable.
TX
RX
TXRDY
RXRDY
wrptr
rdptr
At Least One
At Least One
Location Filled
Location Filled
TXRDY
RXRDY
FIFO Empty
FIFO Empty
wrptr
rdptr
Figure 7. TXRDY and RXRDY in DMA Mode 0/FIFO Disable
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
