SLLS177H − MARCH 1994 − REVISED JANUARY 2006
TL16C550C, TL16C550CI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
Terminal Functions
TERMINAL
NAME
A0
A1
A2
ADS
NO.
N†
28
27
26
25
NO.
FN
31
30
29
28
NO.
PT
28
27
26
24
I/O
I
DESCRIPTION
Register select. A0 −A2 are used during read and write operations to select the ACE register to read
from or write to. Refer to Table 1 for register addresses and refer to ADS description.
Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal
select logic directly; when ADS is high, the register select and chip select signals are held at the logic
levels they were in when the low-to-high transition of ADS occurred.
Baud out. BAUDOUT is a 16
×
clock signal for the transmitter section of the ACE. The clock rate is
established by the reference oscillator frequency divided by a divisor specified by the baud generator
divisor latches. BAUDOUT may also be used for the receiver section by tying this output to RCLK.
Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE. When any
of these inputs are inactive, the ACE remains inactive (refer to ADS description).
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of
the modem status register. Bit 0 (∆ CTS) of the modem status register indicates that CTS has changed
states since the last read from the modem status register. If the modem status interrupt is enabled when
CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used
in the auto-CTS mode to control the transmitter.
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.
I
BAUDOUT
15
17
12
O
CS0
CS1
CS2
CTS
12
13
14
36
14
15
16
40
9
10
11
38
I
I
D0
D1
D2
D3
D4
D5
D6
D7
DCD
1
2
3
4
5
6
7
8
38
2
3
4
5
6
7
8
9
42
43
44
45
46
47
2
3
4
40
I/O
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)
of the modem status register. Bit 3 (∆ DCD) of the modem status register indicates that DCD has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when DCD changes levels, an interrupt is generated.
Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable
an external transceiver.
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of
the modem status register. Bit 1 (∆ DSR) of the modem status register indicates DSR has changed
levels since the last read from the modem status register. If the modem status interrupt is enabled when
DSR changes levels, an interrupt is generated.
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to
establish communication. DTR is placed in the active level by setting the DTR bit of the modem control
register. DTR is placed in the inactive level either as a result of a master reset, during loop mode
operation, or clearing the DTR bit.
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.
Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available
or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status
interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master
reset.
Master reset. When active (high), MR clears most ACE registers and sets the levels of various output
signals (refer to Table 2).
DDIS
DSR
23
37
26
41
22
39
O
I
DTR
33
37
33
O
INTRPT
30
33
30
O
MR
35
39
35
I
The N package is
Not Recommended for New Designs.
6
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•
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