ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆ ꢄ ꢇ ꢀ ꢁ ꢂꢃ ꢄꢅ ꢅꢆ ꢄꢈ
ꢉꢊ ꢋꢌꢄꢍꢎ ꢏꢌ ꢏꢐ ꢊ ꢄꢏ ꢑ ꢑꢐꢌ ꢈꢄꢉꢀ ꢈꢏ ꢌꢊ ꢒ ꢁꢒ ꢑ ꢒꢌ ꢀ
ꢓ ꢈꢀ ꢍ ꢉꢐꢀꢏ ꢔꢁ ꢏ ꢓ ꢄꢏ ꢌ ꢀꢎ ꢏꢁ
ꢕ
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 8)
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN
MAX
UNIT
t
t
Delay time, RCLK to sample
t
8
10
ns
d12
SCD
Delay time, stop to set INTRPT or read
RBR to LSI interrupt or stop to RXRDY↓
8, 9, 10,
11, 12
RCLK
cycle
t
1
d13
SINT
RINT
8, 9, 10,
11, 12
t
Delay time, read RBR/LSR to reset INTRPT
t
C
= 75 pF
L
70
ns
d14
NOTE 8: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification
register or line status register).
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN MAX
UNIT
baudout
cycles
t
Delay time, initial write to transmit start
t
13
8
8
24
d15
IRS
baudout
cycles
t
t
t
Delay time, start to INTRPT
t
13
13
13
10
50
34
d16
d17
d18
STI
Delay time, WR (WR THR) to reset INTRPT
t
C
= 75 pF
ns
HR
L
baudout
cycles
†
Delay time, initial write to INTRPT (THRE )
t
SI
16
†
Delay time, read IIR to reset INTRPT
(THRE )
t
t
t
t
13
C
C
C
= 75 pF
= 75 pF
= 75 pF
35
35
9
ns
ns
d19
d20
d21
IR
L
L
L
†
Delay time, write to TXRDY inactive
Delay time, start to TXRDY active
t
t
14,15
14,15
WXI
baudout
cycles
SXA
†
THRE = transmitter holding register empty; IIR = interrupt identification register.
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C = 75 pF
L
PARAMETER
ALT. SYMBOL
FIGURE
16
MIN
MAX
50
UNIT
ns
t
t
t
Delay time, WR MCR to output
t
MDO
d22
d23
d24
Delay time, modem interrupt to set INTRPT
Delay time, RD MSR to reset INTRPT
t
16
35
ns
SIM
t
16
40
ns
RIM
baudout
cycles
t
t
t
t
t
Delay time, CTS low to SOUT↓
17
18
18
19
19
24
2
d25
d26
d27
d28
d29
baudout
cycles
Delay time, RCV threshold byte to RTS↑
Delay time, read of last byte in receive FIFO to RTS↓
Delay time, first data bit of 16th character to RTS↑
Delay time, RBRRD low to RTS↓
baudout
cycles
2
baudout
cycles
2
baudout
cycles
2
11
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